Thin film transistor including a lightly doped amorphous silicon channel layer

ABSTRACT

A thin film transistor (TFT) is provided. The thin film transistor (TFT) comprises a substrate, a gate, an inter-gate dielectric layer, a channel layer and source/drain regions. A gate is formed over the substrate. An inter-gate dielectric layer is formed over the substrate covering the gate. A doped amorphous silicon layer is formed over a portion of the inter-gate dielectric layer at least covering the gate to serve as channel layer. Source/drain regions are formed over the channel layer.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional application of patent application Ser. No.10/711,509, filed on Sep. 23, 2004, which is a continuation-in-part ofprior applications Ser. No. 10/777,564, filed on Feb. 11, 2004. Theentirety of each of the above-mentioned patent applications is herebyincorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a thin film transistor (TFT).More particularly, the present invention generally relates to a thinfilm transistor (TFT) having a lightly doped amorphous silicon channellayer.

2. Description of the Related Art

In recent years, a variety of macromedia electronic devices and productsare drastically developed due to the rapid development of thesemiconductor device and the user interface of the device.Conventionally, since the cathode ray tube (CRT) display device islow-cost and has high performance, it is widely used display device.However, as to the display device of the personal computer, the cathoderay tube (CRT) display has the disadvantages of large size and highpower consumption. Accordingly, the liquid crystal display (LCD) beingsmall, lightweight, use low operational voltage, low power consumption,radiation free and environmentally friendly, gradually replaced theconventional CRT display. In recent years, the liquid crystal display(LCD), for example, the thin film transistor (TFT) liquid crystaldisplay (LCD) has become the main stream of the display devices.

In general, the conventional thin film transistor (TFT) may beclassified into amorphous silicon thin film transistor (TFT) andpolysilicon thin film transistor (TFT). It is noted that, the technologyof low temperature polysilicon (LTPS) is different from the technologyof conventional amorphous silicon (α-Si). In the low temperaturepolysilicon (LTPS) technology, the electron mobility can be enhanced tomore than 200 cm²/V-sec. Therefore, the size of the thin film transistor(TFT) can be minimized, the aperture ratio of the display can beenhanced, and the power consumption can be reduced. However, because ofthe manufacturing process of the amorphous silicon thin film transistor(TFT) technology is well developed, simple and low-cost, the amorphoussilicon thin film transistor (TFT) technology is still the main streamof the array of the display device.

FIG. 1 is a cross-sectional view schematically illustrating thestructure of conventional amorphous silicon thin film transistor (TFT).Referring to FIG. 1, the thin film transistor (TFT) 100 includes asubstrate 110, a gate 120, an inter-gate dielectric layer 130, a channellayer 140 and source/drain regions 150. The gate 120 is disposed on thesubstrate 110. The inter-gate dielectric layer 130 is disposed on thesubstrate and covers the gate 120. The channel layer 140 is disposed ona portion of the inter-gate dielectric layer 130 that at least coversthe gate 120. The source/drain regions 150 are disposed on the channellayer 140 and are separated by a distance. When the gate 120 operates tosupply an operating voltage to the channel layer 140, the source/drainregions 150 are electrically connected by the channel layer 140.

The manufacturing method of the channel layer 140 of the conventionalthin film transistor (TFT) 100 includes the following steps. First, thesubstrate 110 is transported into a reaction chamber (not shown) and thesubstrate is subjected to a reaction gas mixture comprising of silane(SiH₄) and hydrogen (H₂) in the reaction chamber to form an intrinsicamorphous silicon layer. Next, the amorphous silicon layer is patternedto form the channel layer 140.

Accordingly, because the channel layer of the thin film transistor (TFT)is an intrinsic amorphous silicon layer, the electron mobility and theturning-on-current are not high enough when the thin film transistor isoperated.

SUMMARY OF THE INVENTION

Accordingly, one object of the present invention is to provide a thinfilm transistor. (TFT) and the manufacturing method thereof to increasethe turning-on-current and the electron mobility of the channel regionof the thin film transistor (TFT).

In accordance with the above objects and other advantages of the presentinvention, a manufacturing method of thin film transistor (TFT) isprovided. The manufacturing method includes the following steps. First,a gate is formed over a substrate. Next, an inter-gate dielectric layeris formed over the substrate covering the gate. Next, a channel layer isformed covering over a portion of the inter-gate dielectric layer atleast covering the gate. The channel layer comprises a lightly dopedamorphous silicon layer. Next, source/drain regions are formed over thechannel layer, wherein the source/drain regions are separated by adistance.

In an embodiment of the present invention, the channel layer comprisesan N-type lightly doped amorphous silicon layer. In another embodimentof the invention, the channel layer may comprise a P-type lightly dopedamorphous silicon layer.

In an embodiment of the present invention, the channel layer, forexample but not limited to, doped with phosphorous atoms, and aconcentration of phosphorous atoms in the channel layer is in a range ofabout 1E17 atom/cm³ to about 1E18 atom/cm³. In another embodiment of theinvention, the channel layer is, for example but not limited to, dopedwith boron atoms, and a concentration of boron atoms in the channellayer is in a range of about 1E16 atom/cm³ to about 5E17 atom/cm³.

In an embodiment of the present invention, the channel layer is formedby performing, for example but not limited to, a chemical vapordeposition (CVD) process using a reaction gas mixture comprising silane(SiH₄), hydrogen and phosphine (PH₃), wherein a effective content ratioof phosphine (PH₃) is in a range of about 2.8E-7 to about 8E-6, whereinthe effective content ratio of the phosphine (PH₃) is equal to the ratioof the content of phosphine (PH₃) to the total content of silane (SiH₄),hydrogen (H₂) and phosphine (PH₃).

In another embodiment of the present invention, the channel layer isformed by performing, for example but not limited to, a chemical vapordeposition (CVD) process using a reaction gas mixture comprising silane(SiH₄), hydrogen (H₂) and boroethane (B₂H₆), wherein a effective contentratio of the boroethane (B₂H₆) is in a range of about 5E-7 to about1E-5, and wherein the effective content ratio of the boroethane (B₂H₆)is equal to the ratio of the content of boroethane (B₂H₆) to the totalcontent of silane (SiH₄), hydrogen (H₂) and boroethane (B₂H₆).

In an embodiment of the present invention, the channel layer is formedby, for example but not limited to, forming a first lightly dopedsub-amorphous silicon layer over a portion of the inter-gate dielectriclayer at a first deposition rate, and forming a second lightly dopedsub-amorphous silicon layer over the first lightly doped sub-amorphoussilicon layer at a second deposition rate, wherein the first depositionrate is lower than the second deposition rate.

In an embodiment of the present invention, the method further includes,for example but not limited to, a step of forming an ohmic contact layerover the channel layer between the steps of forming the channel layerand the step of forming the source/drain regions.

In an embodiment of the present invention, the method further includes,for example but not limited to, a step of forming a protection layerover the substrate covering the source/drain regions, the channel layerand the inter-gate dielectric layer.

In accordance with above objects and other advantages of the presentinvention, a thin film transistor (TFT) is provided. The thin filmtransistor (TFT) includes a substrate, a gate, an inter-gate dielectriclayer, a channel layer and source/drain regions. The gate is disposedover the substrate, and the inter-gate dielectric layer is disposed onthe substrate and covers the gate. The channel layer is disposed over aportion of the inter-gate dielectric layer, wherein the channel coversthe gate. The channel layer comprises a lightly doped amorphous siliconlayer. The source/drain regions are disposed over the channel layer,wherein the source/drain regions are separated by a distance.

In an embodiment of the present invention, the channel layer comprisesan N-type lightly doped amorphous silicon layer. In another embodimentof the invention, the channel layer may comprise a P-type lightly dopedamorphous silicon layer.

In an embodiment of the present invention, the channel layer is, forexample but not limited to, doped with phosphorous atoms, and aconcentration of phosphorous atoms in the channel layer is in a range ofabout 1E17 atom/cm³ to about 1E18 atom/cm³. In another embodiment of theinvention, the channel layer is, for example but not limited to, dopedwith boron atoms, and a concentration of boron atoms in the channellayer is in a range of about 1E16 atom/cm³ to about 5E17 atom/cm³.

In an embodiment of the present invention, the method of forming thechannel layer includes, for example but not limited to, a first lightlydoped sub-amorphous silicon layer and a second lightly dopedsub-amorphous silicon layer. Wherein the first lightly dopedsub-amorphous silicon layer is formed over a portion of the inter-gatedielectric layer at a first deposition rate, and the second lightlydoped sub-amorphous silicon layer is formed over the first lightly dopedsub-amorphous silicon layer at a second deposition rate. Furthermore,the second deposition rate is higher than the first deposition rate.

In an embodiment of the present invention, the TFT further includes, forexample but not limited to, an ohmic contact layer disposed between thechannel layer and the source/drain.

In an embodiment of the present invention, the TFT further includes, forexample but not limited to, a protection layer disposed over thesubstrate covering the source/drain regions, the channel layer and theinter-gate dielectric layer.

According to an aspect of the present invention, a lightly dopedamorphous silicon layer is provided as a channel layer achieve at leastthe advantages of increased electron mobility of the channel layer andthereby increase the turning-on-current of thin film transistor (TFT)without increasing the leakage current, and the improvement of the ohmiccontact between the channel layer and the source/drain regions.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The following drawings illustrateembodiments of the invention and, together with the description, serveto explain the principles of the invention.

FIG. 1 is a cross-sectional view schematically illustrating thestructure of a conventional amorphous silicon thin film transistor(TFT).

FIG. 2A to FIG. 2F are cross-sectional views schematically illustratingthe process flow of a process of forming a thin film transistor (TFT)according to a preferred embodiment of the present invention.

FIG. 3 is a plot illustrating the relationship between theturning-on-current and the effective content ratio of the phosphine(PH3) in the process of forming the thin film transistor (TFT) accordingto one of the preferred embodiment of the present invention.

FIG. 4 is a plot illustrating the relationship between the electronmobility and the effective content ratio of the phosphine (PH3) in theprocess of forming the thin film transistor (TFT) according to one ofthe preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as limited to theembodiments set forth herein; rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. Likenumbers refer to like elements throughout.

FIG. 2A to FIG. 2F are cross-sectional views schematically illustratingthe process flow of a process of forming a thin film transistor (TFT)according to a preferred embodiment of the present invention. As shownin FIG. 2A, a gate 220 is formed over a substrate 210. Next, aninter-gate dielectric layer 230 is formed over the substrate 210 atleast covering the gate 220. The method of forming the gate 220includes, for example but not limited to, forming a first conductivelayer (Metal 1) over the substrate 210 by performing a sputteringprocess, and then performing well known photolithography and etchingprocess to form the gate 220. The inter-gate dielectric layer 230 can beformed by, for example but not limited to, performing a plasma enhancechemical vapor deposition (PECVD) process.

Furthermore, the substrate 210 includes, for example but not limited to,a glass substrate, a transparent plastic substrate or a substratecomposed of any transparent material. The material of the gate 220includes, for example but not limited to, tantalum (Ta), chromium (Cr),molybdenum (Mo), titanium (Ti) or aluminum (Al) or other conductivematerial. The material of the inter-gate dielectric layer 230 includes,for example but not limited to silicon nitride (SixNy), siliconoxynitride (SiON), silicon oxide (SiOx) or other dielectric material.

Next, as shown in FIG. 2B, a channel layer 240 is formed over a portionof the inter-gate dielectric layer 230 at least covering the gate 220.The channel layer 240 comprises, for example but not limited to, lightlydoped amorphous silicon layer, wherein the doped amorphous silicon layercomprises an N-type lightly doped amorphous silicon layer or P-typelightly doped amorphous silicon layer. The channel layer 240 can beformed by performing, for example but not limited to, a chemical vapordeposition (CVD) process. The CVD process includes, for example,transporting the substrate 210 into a reaction chamber (not shown).Next, a reaction gas mixture is charged into the reaction chamber,wherein the reaction gas mixture comprises, for example but not limited,silane (SiH₄), hydrogen (H₂) and phosphine (PH₃). Alternatively, thereaction gas mixture may comprise silane (SiH₄), hydrogen (H₂) andboroethane (B₂H₆). For the reaction gas comprising phosphine (PH₃), theeffective content ratio of the phosphine (PH₃) is, for example but notlimited to, in a range of about 2.8E-7 to about 8E-6. And, for thereaction gas comprising boroethane (B₂H₆), the effective content ratioof the boroethane (B₂H₆) is, for example but not limited to, in a rangeof about 5E-7 to about 1E-5. The effective content ratio of thephosphine (PH₃) is equal to the ratio of the content of phosphine (PH₃)to the total content of silane (SiH₄), hydrogen and phosphine (PH₃). Theeffective content ratio of the boroethane (B₂H₆) is equal to the ratioof the content of boroethane (B₂H₆) to the total content of silane(SiH₄), hydrogen and boroethane (B₂H₆).

In an embodiment of the present invention, the channel layer 240 is, forexample but not limited to, doped with phosphorous atoms. Theconcentration of phosphorous atoms is, for example but not limited to,in a range of about 1E17 atom/cm³ to 1E18 atom/cm³. Alternatively, thechannel layer 240 is, for example but not limited to, doped with boronatoms. The concentration of boron atoms is, for example but not limitedto, in a range of about 1E16 atom/cm³ to 5E17 atom/cm³.

The method of forming the channel layer 240 is described as follows.First, a first lightly doped sub-amorphous silicon layer 242 is formedover a portion of the inter-gate dielectric layer 230 at least coveringthe gate 220 at a first deposition rate. Next, a second lightly dopedsub-amorphous silicon layer 244 is formed over the first lightly dopedsub-amorphous silicon 242 at a second deposition rate. In an embodimentof the invention, the first deposition rate is, lower than the seconddeposition rate.

Next, as shown in FIG. 2C, an ohmic contact layer 250 is formed over thechannel layer 240, wherein the ohmic contact layer 250 has an excellentcontact with a metal surface. The method of forming the ohmic contactlayer 250 includes, for example but not limited to, performing an ionimplant process to implant N-type ions into the amorphous silicon layer.

Next, as shown in FIG. 2D, source/drain regions 260 are formed over thechannel layer 240. The forming method of source/drain regions 260includes, for example but not limited to, first forming a secondconductive layer (Metal 2) over the substrate 210, and then performingthe well known photolithography and etching process to form thesource/drain regions 260. The material of the source/drain 260 includes,for example but not limited to, tantalum (Ta), chromium (Cr), molybdenum(Mo), titanium (Ti), aluminum (Al), or other conductive material.

Next, as shown in FIG. 2E, a protection layer 270 is formed over thesubstrate 210 to cover the source/drain regions 260, the channel layer240 and the inter-gate dielectric layer 230. The protection layer 270comprises an opening 272 exposing a portion of the source/drain region260 there-within.

Next, as shown in FIG. 2F, a transparent conductive layer 280 is formedover the protection layer 270 and electrically connected to thesource/drain region 260 through the opening 272. The transparentconductive layer 280 includes, for example but not limited to, a pixelelectrode. The material of the transparent conductive layer 280includes, for example but not limited to, indium tin oxide (ITO),strontium tin oxide (STO), or other transparent conductive material.

Referring to FIG. 2E, a structure of the thin film transistor (TFT) 200of the present invention is shown. The TFT comprises a substrate 210, agate 220, an inter-gate dielectric layer 230, a channel layer 240 andsource/drain regions 260. The gate 220 is disposed over the substrate210. The inter-gate dielectric layer 230 is disposed over the substrate210 and covers the gate 220. The channel layer 240 is disposed over aportion of the inter-gate dielectric layer 230 at least covering thegate 210. The material of the channel layer 240 includes, for example, alightly doped amorphous silicon layer. The source/drain regions 260 aredisposed over the channel layer 240, wherein the source/drain areseparated by a distance.

Furthermore, the channel layer 240 comprises, for example but notlimited to, an N-type lightly doped amorphous silicon layer or P-typelightly doped amorphous silicon layer.

Furthermore, the channel layer 240 is, for example but not limited to,doped with phosphorous atoms, and the concentration of phosphorous atomsin the channel layer 240 is, for example but not limited to, in a rangeof about 1E17 atom/cm³ to about 1E18 atom/cm³. Alternatively, thechannel layer 240 is, for example but not limited to, boron atoms, andthe concentration of boron atoms in the channel layer 240 is, forexample but not limited to, in a range of about 1E16 atom/cm³ to about5E17 atom/cm³.

Moreover, the channel layer 240 can be formed by, for example but notlimited to, sequentially forming a first lightly doped sub-amorphoussilicon layer 242 and a second lightly doped sub-amorphous silicon layer244 over the inter-gate dielectric layer 220. The first lightly dopedsub-amorphous silicon layer 242 is disposed, for example but not limitedto, on a portion of the inter-gate dielectric layer 220 that at leastcovers the gate 210. The second lightly doped sub-amorphous siliconlayer 244 is disposed, for example but not limited to, on the firstlightly doped sub-amorphous silicon layer 242.

Moreover, the thin film transistor (TFT) 210 further includes, forexample but not limited to, an ohmic contact layer 250 and a protectionlayer 270 formed over the substrate 210. The ohmic contact layer 250 isdisposed, for example but not limited to, between the channel layer 240and the source/drain regions 260 to enhance the ohmic contact thechannel layer 240 and the source/drain regions 260. The protection layer270 is disposed on, for example but not limited to, the substrate 210,and the protection layer 270 covers the source/drain regions 260, thechannel layer 240 and the inter-gate dielectric layer 220.

However, it is noted that, the above-described thin film transistor(TFT) and the manufacturing method thereof of the embodiments of thepresent invention is provided as exemplary embodiments of the invention.Further, the use of channel layer composed of lightly doped amorphoussilicon layer in a thin film transistor (TFT) and the process of formingthe same in a TFT falls within the scope of the present invention.

FIG. 3 is a plot illustrating the relationship between theturning-on-current and the effective content ratio of phosphine (PH₃) inthe process of forming the thin film transistor (TFT) according to oneof the preferred embodiment of the present invention. FIG. 4 is a plotillustrating the relationship between the electron mobility and theeffective content ratio of phosphine (PH₃) in the process of forming thethin film transistor (TFT) according to one of the preferred embodimentof the present invention. As shown in FIG. 3, the turning-on-current ofthe thin film transistor (TFT) increases drastically with the increasingeffective content ratio of the phosphine (PH₃) in presence of thechannel layer. As shown in FIG. 4, the electron mobility of the channellayer of the thin film transistor (TFT) drastically increases with theincreasing effective content ratio of the phosphine (PH₃) in presence ofthe channel layer. In FIG. 3 and FIG. 4, the parameter (2.9/2.8) meansthat the effective content ratio of the phosphine (PH₃) is 2.9*1E-7 whenfabricating the first lightly doped sub-amorphous layer, and theeffective content ratio of the phosphine (PH₃) is 2.8*1E-7 whenfabricating the second lightly doped sub-amorphous layer. Similarly, theparameter (5.7/5.6) means that the effective content ratio of thephosphine (PH₃) is 5.7*1E-7 when fabricating the first lightly dopedsub-amorphous layer, and the effective content ratio of the phosphine(PH₃) is 5.6*1E-7 when fabricating the second lightly dopedsub-amorphous layer. Moreover, the rest parameters such as (8.6/8.3),(11.4/11.1), (54.7/44.4), (80/77.8) and (108.6/105.6) are explained inthe same way. For example, the effective content ratio of phosphine(PH₃) X is calculated as follow. X_(PH3)=(R_(PH3)*W_(PH3))/((R_(PH3)*W_(PH3))+(R_(H2)*W_(H2))+(R_(SiH4)*W_(SiH4))), wherein R_(PH3) is theflow rate of phosphine; W_(PH3) is the weight percent of phosphine;R_(H2) is the flow rate of hydrogen; W_(H2) is the weight percent ofhydrogen; R_(siH4) is the flow rate of silane; and W_(SiH4) is theweight percent of silane.

Furthermore, the TFT of the present invention was tested, the testresults reveal that the TFT of the present invention do not have excessthe leakage current, and the ohmic contact between the channel layer andthe source/drain is substantially improved.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A thin film transistor (TFT), comprising: a substrate; a gate,disposed over the substrate; an inter-gate dielectric layer, disposedover the substrate covering the gate; a channel layer, disposed over aportion of the inter-gate dielectric layer, at least over the gate,wherein the channel layer comprises a lightly doped amorphous siliconlayer; and source/drain regions, disposed over the channel layer,wherein the source/drain regions are separated by a distance.
 2. Thethin film transistor (TFT) of claim 1, wherein the channel layercomprises an N-type lightly doped amorphous silicon layer.
 3. The thinfilm transistor (TFT) of claim 1, wherein the channel layer comprises aP-type lightly doped amorphous silicon layer.
 4. The thin filmtransistor (TFT) of claim 1, wherein the channel layer is doped withphosphorous atoms, and a concentration of phosphorous atoms is in arange of about 1E17 atom/cm³ to about 1E18 atom/cm³.
 5. The thin filmtransistor (TFT) of claim 1, wherein the channel layer is doped withboron atoms, and a concentration of boron atoms is in a range of about1E16 atom/cm³ to about 5E17 atom/cm³.
 6. The thin film transistor (TFT)of claim 1, wherein the lightly doped amorphous silicon layer comprises:a first lightly doped sub-amorphous silicon layer, disposed over aportion of the inter-gate dielectric layer; and a second lightly dopedsub-amorphous silicon layer, disposed over the first lightly dopedsub-amorphous silicon layer, wherein the first lightly dopedsub-amorphous silicon layer is formed at a first deposition rate, andthe second lightly doped sub-amorphous silicon layer is formed at asecond deposition rate higher than the first deposition rate.
 7. Thethin film transistor (TFT) of claim 1, further comprising an ohmiccontact layer between the channel layer and the source/drain regions. 8.The thin film transistor (TFT) of claim 1, further comprising aprotection layer over the substrate, wherein the protection layer coversthe source/drain regions, the channel layer and the inter-gatedielectric layer.